1. Field of the Invention
The present invention relates to a package substrate manufactured using an electrolytic leadless plating process, and a method for manufacturing the same. More particularly, the present invention relates to a package substrate of, for example, a ball grid array (BGA) type or a chip scale package (CSP) type, manufactured by electrolytically plating Au in a semi-additive manner without using any plating lead line on wire bonding pads to be connected with a semiconductor chip mounted on a base substrate, and solder ball pads, and a method for manufacturing the same.
2. Description of the Related Art
In spite of the recent tendency of integrated circuits to have a light, thin, simple and miniature structure, integrated circuit packages rather tend to have an increased number of leads extending outwardly therefrom. One method capable of solving problems caused by installation of a number of leads on a carrier for a miniature package is to use a carrier having a pin grid array (PGA). Although such a PGA carrier can have a number of leads while having a miniature size, it has a drawback in that its pins or leads may be easily broken due to their low strength, or involves a limitation of high-density integration.
In order to solve such drawbacks involved with PGA, use of BGA package substrates has recently been generalized. The reason why such a BGA package substrate has been generally used is that it is possible to easily achieve a high-density integration of the substrate in accordance with use of solder balls finer than pins. Such a BGA package substrate is mainly used for a package substrate adapted to mount a semiconductor chip thereon.
A conventional example of such a BGA package will be described in brief hereinafter. Referring to FIG. 1, a conventional BGA package is shown which has a structure formed with solder balls 8, in place of conventional pins. In order to fabricate this structure, a plurality of copper clad laminates (CCLs) 4 are first prepared. An inner-layer circuit is formed at each of the CCLs 4 in accordance with a well-known photolithography process. The CCLs 4 are then laminated in accordance with a pressing process. Thereafter, via holes 2 are formed at the laminated CCL structure in order to electrically connect the inner-layer circuits of respective CCLs. The via holes 2 are plated with a copper film 3 so that they are electrically connected. An outer-layer circuit 6 is subsequently formed at the outermost CCL 4 of the laminated CCL structure in accordance with a photolithography process. The outer-layer circuit 6 has bond fingers 1 to be connected with a semiconductor chip mounted on the laminated CCL structure. Thereafter, solder ball pads 7, a solder mask 5, and solder balls 8 are sequentially formed at a surface of the laminated CCL structure opposite to the outer-layer circuit 6.
Meanwhile, Au-plating lead lines are formed in order to perform a plating process adapted to obtain improved electrical connections of the pads 7 with both the bond fingers 1 connected to the semiconductor chip and the solder balls 8. Each Au-plating lead line is connected to an associated one of the pads 7 connected to respective solder balls 8. Although not shown, the Au-plating lead lines are also connected to the bond fingers 1 via the pads 7 and via holes 2, respectively. FIG. 2 is a plan view illustrating the package substrate plated using conventional plating lead lines. As shown in FIG. 2, plating lead lines 9 are connected to respective solder ball pads 7 at which respective solder balls 8 are formed. The area where the plating lead lines 9 are formed corresponds to the portion A of FIG. 1. Substantially, there is a limitation of high-density integration in designing a circuit, due to such plating lead lines.
On the other hand, an integrated circuit (IC) chip is mounted on the CCL 4 formed with the outer-layer circuit 6, while being connected with the outer-layer circuit 6 by conductive lines. An encapsulant is coated over the CCL 4 to protect the CCL 4 from the surroundings. Thus, the BGA package substrate 10 is connected with a main circuit board by the solder balls 8 formed at the pads 7 of the pad-carried CCL 4, as compared to a PGA substrate which is connected to a main circuit board by pins. For this reason, it is possible to easily miniaturize BGAs, as compared to PGAs. Accordingly, the BGA substrate 10 can achieve high-density integration.
However, the above mentioned conventional BGA package substrate 10 involves a problem in that it is difficult to achieve high-density integration of the Au-plating lead lines adapted to carry out an Au plating process for the bond fingers 1 and pads 7 because the pitch of the solder balls 8 in the BGA package substrate, that is, the space between adjacent solder balls, is rendered to be very small due to high-density integration of circuits and miniaturization of devices using such circuits, and because of high-density integration of circuits arranged around the bond fingers 1 of the outer-layer circuit mounted with the semiconductor chip thereon.
Now, a conventional method for manufacturing a package substrate plated with Au using plating lead lines will be described with reference to FIGS. 3a to 3i. 
First, a plurality of through holes, that is, via holes, 12, are formed at a base substrate 11 (FIG. 3a). A copper film 13 is plated in accordance with an electroless plating process to cover the entire surface of the base substrate 11 and the inner surface of each through hole 12 (FIG. 3b).
In order to manufacture a package substrate provided with desired circuits, a resist 14 for a copper plating process is then coated over the plated upper and lower surfaces of the base substrate 11. The resist 14 is subsequently subjected to exposure and development processes so that it is patterned in such a fashion that it is removed from portions of the copper-plated surfaces of the base substrate 11 respectively corresponding to regions where desired circuit patterns are to be plated (FIG. 3c). The via holes 12 are formed by perforating through holes into the base substrate 11 using a mechanical drill. For the resist 14, a dry film is typically used.
Thereafter, circuit patterns 15 are formed, in accordance with a plating process, on the copper-plated surface portions of the base substrate 11 corresponding to respective regions where the resist 14 is not present (FIG. 3d). The remaining resist 14 is then completely removed using a stripping solution (FIG. 3e).
Subsequently, portions of the copper film 13 exposed on the base substrate in accordance the removal of the resist 14 are removed using an etchant (FIG. 3f). In FIG. 3f, the reference numeral 16 denotes regions where the copper film 13 is etched by the etchant.
A solder resist 17 is then coated over the entire surface of the resultant structure, and subjected to exposure and development processes so that it is removed from regions where Au is to be plated in accordance with an electrolytic plating process, that is, wire bonding pads and solder ball pads are to be formed (FIG. 3g).
An Au film 18 is plated on wire bonding pads and solder ball pads included in respective circuits by applying current to the previously formed plating lead lines. The plating of the Au film 18 may be achieved in accordance with an electrolytic Ni—Au plating process. Typically, the thickness of the plated Au film 18 is about 0.5 to 1.0 μm (FIG. 3h).
Generally, an electrolytic Au plating process is mainly used for metal finishing of the surface of a package substrate on which a semiconductor chip is mounted, because it is superior over an electroless Au plating process in terms of reliability. For such an electrolytic Au plating process, however, it is necessary to design the package substrate to be provided with plating lead lines. For this reason, there is a reduction in line density. Such a reduced line density causes a problem in manufacturing a circuit having a high-density integration.
Thereafter, the plating lead lines are cut using a router or a dicing process (FIG. 3i). In FIG. 3i, the reference numeral 19 denotes a region where the dicing process is carried out. That is, the plating lead lines are cut using the router or dicing process, after completion of the electrolytic Au plating process. However, the plating lead lines are incompletely removed from the package substrate. The residues of the plating lead lines may cause noise during transmission of electrical signals in the circuits provided at the package substrate. As a result, there is a degradation in electrical performance.
Meanwhile, recently, manufacturers of package substrates have made an effort to develop a technique capable of carrying out an electrolytic Au plating process without using any plating lead line. In the above mentioned conventional electrolytic Au plating process, both the wire bonding pads and the solder ball pads are plated with Au to the same thickness (in most cases, 0.5 to 1.5 μm). In the case of the solder ball pads, however, such a thickness is excessive, as compared to an appropriate thickness of 0.03 to 0.25 μm. For this reason, there is a problem associated with the reliability of the bonding of solder bails.